TILE64
Tilera多核处理器是并行计算领域的又一革新，它通过多项独有的技术创新，将嵌入式应用的运算性能提升到了前所未有的高度。
TILE64TM是Tilera推出的第一款多核处理器产品，它由64个相同的处理器核（Tile）组成，每个Tile都是一个完整的全功能处理器，拥有自己的L1 & L2 cache，并通过内置的无阻塞交换矩阵与其他Tile互联，从而形成一个高速、无阻塞的Mesh网络，即Tilera独有的iMeshTM片上网络。此外，得益于Tilera独有的DDCTM（Dynamic Distributed Cache动态分布式缓存）技术，TILE64TM上的cache将具有2倍于其他多核处理器的使用性能。
TILE64TM集成了一套完备的内存与I/O控制器，不再需要借助于传统的南北桥芯片来实现外部数据的接入，从而大大降低了硬件系统的设计复杂度与成本。
TILE64TM支持标准的C/C++编程，对于开发者而言，这意味着绝大多数已有的软件或开源代码只需经过简单的移植即可在TILE64TM平台上运行。此外，TILE64TM还支持同时运行多个操作系统实例，既可以每个Tile运行一个独立的操作系统，也可以几个Tile合起来运行一个支持多进程的操作系统，如SMP Linux，当然，部分或全部Tile还可以在完全无操作系统的模式下运行，这非常适合数据平面的大数据量处理，最大限度消除操作系统对处理性能的消耗。
TILE64TM非常适合大规模应用于如下领域：
Advanced Networking:
The TILE64 processor provides the Ethernet line interfaces as well as the entire data plane processing for intelligent network services such as:
- Unified Threat Management (UTM)
- Network Security Appliances
- In-line L4-7 deep packet inspection
- Network Monitoring & Forensics
Digital Video:
The TILE64 processor also excels at digital video processing, easily taking the place of multiple DSPs as well as the networking components for:
- Media 'Head-End' services
- Video-on-Demand (VoD) Servers
- Video surveillance
- Video Conferencing
| Feature | Enables | |
| Massively Scalable Performance | • 8 X 8 grid of identical, general purpose processor cores (tiles) • 3-way VLIW pipeline for instruction level parallelism • 5 Mbytes of on-chip Cache • Up to 443 billion operations per second (BOPS) • 31 Tbps of on-chip mesh interconnect • Up to 50 Gbps of I/O bandwidth |
• 10 Gbps Snort® processing • 20 Gbps iptables (firewall) • 20+ Gbps nProbe • 16 X 16 SAD at 540 MBlocks/s • H.264 HD video encode: 2+ streams of 720p |
| Power Efficiency | • 500MHz – 866MHz operating frequency • 15 – 22W @ 700MHz all cores active • Idle Tiles can be put into low-power sleep mode • Power efficient inter tile communications |
• Highest performance per watt • Simple thermal management & power supply design • Small System form factor • Lower operating cost |
| Integrated Solution | • Four DDR2 memory controllers with optional ECC • Two XAUI configurable MAC or PHY interfaces • Two 4-lane 10Gbps PCI-e MAC/PHY interfaces • Two GbE MAC interfaces • Flexible I/O interface |
• Reduces BOM cost – standard interfaces included on-chip • Dramatically reduced board real estate • Direct interface to leading L2-L3 switch vendors |
| Ease of Programming | • ANSI standard C / C++ compiler • Supports SMP Linux with 2.6 kernel • iLib™ API's for efficient inter-tile communication • Advanced profiling and debugging designed for multicore programming |
• Run off-the-shelf C and C++ programs • Leverage investment in existing code • Reduce debug and optimization time • Faster time to production code • Standard multicore communication mechanisms |
